SH7619_09 Datasheet, PDF (555/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.4 Register Descriptions
The HIF has the following registers.
• HIF index register (HIFIDX)
• HIF general status register (HIFGSR)
• HIF status/control register (HIFSCR)
• HIF memory control register (HIFMCR)
• HIF internal interrupt control register (HIFIICR)
• HIF external interrupt control register (HIFEICR)
• HIF address register (HIFADR)
• HIF data register (HIFDATA)
• HIF boot control register (HIFBCR)
• HIFDREQ trigger register (HIFDTR)
• HIF bank interrupt control register (HIFBICR)
17.4.1 HIF Index Register (HIFIDX)
HIFIDX is a 32-bit register used to specify the register read from or written to by an external
device when the HIFRS pin is held low. HIFIDX can be only read by the on-chip CPU. HIFIDX
can be only written to by an external device while the HIFRS pin is driven high.
Initial
Bit Bit Name Value R/W Description
31 to 8 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 515 of 816
REJ09B0237-0600