SH7619_09 Datasheet, PDF (18/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

14.5.3
14.5.4
Conflict between Byte-Write and Count-Up Processes of CMCNT................. 375
Conflict between Write Processes to CMCNT with the
Counting Stopped and CMCOR........................................................................ 375
Section 15 Serial Communication Interface with FIFO (SCIF)........................ 377
15.1 Overview .......................................................................................................................... 377
15.1.1 Features............................................................................................................. 377
15.2 Pin Configuration.............................................................................................................. 380
15.3 Register Description ......................................................................................................... 381
15.3.1 Receive Shift Register (SCRSR) ...................................................................... 382
15.3.2 Receive FIFO Data Register (SCFRDR) .......................................................... 382
15.3.3 Transmit Shift Register (SCTSR) ..................................................................... 382
15.3.4 Transmit FIFO Data Register (SCFTDR)......................................................... 383
15.3.5 Serial Mode Register (SCSMR)........................................................................ 383
15.3.6 Serial Control Register (SCSCR)...................................................................... 386
15.3.7 Serial Status Register (SCFSR) ........................................................................ 390
15.3.8 Bit Rate Register (SCBRR) .............................................................................. 398
15.3.9 FIFO Control Register (SCFCR) ...................................................................... 405
15.3.10 FIFO Data Count Register (SCFDR)................................................................ 408
15.3.11 Serial Port Register (SCSPTR) ......................................................................... 409
15.3.12 Line Status Register (SCLSR) .......................................................................... 413
15.4 Operation .......................................................................................................................... 414
15.4.1 Overview .......................................................................................................... 414
15.4.2 Operation in Asynchronous Mode .................................................................... 416
15.4.3 Synchronous Mode ........................................................................................... 427
15.5 SCIF Interrupts ................................................................................................................. 435
15.6 Serial Port Register (SCSPTR) and SCIF Pins ................................................................. 436
15.7 Usage Notes ...................................................................................................................... 440
Section 16 Serial I/O with FIFO (SIOF) ........................................................... 445
16.1 Features............................................................................................................................. 445
16.2 Input/Output Pins.............................................................................................................. 447
16.3 Register Descriptions........................................................................................................ 448
16.3.1 Mode Register (SIMDR) .................................................................................. 449
16.3.2 Control Register (SICTR)................................................................................. 452
16.3.3 Transmit Data Register (SITDR) ...................................................................... 455
16.3.4 Receive Data Register (SIRDR) ....................................................................... 456
16.3.5 Transmit Control Data Register (SITCR) ......................................................... 457
16.3.6 Receive Control Data Register (SIRCR) .......................................................... 458
16.3.7 Status Register (SISTR).................................................................................... 459
Rev. 6.00 Jul. 15, 2009 Page xvi of xxxviii