SH7619_09 Datasheet, PDF (528/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
No.
Flow Chart
1
Start
Set SIMDR, SISCR, SITDAR, SIRDAR,
SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
3
Set the FSE bit in SICTR to 1
4
Set the TXE and RXE bit in SICTR to 1
SIOF Settings
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
SIOF Operation
Set operation start for baud rate
generator
Set the start for frame synchronous
signal output
Note: Serial clock will not be output from the
pin until communication is actually
started.
Enable transmission and reception Note: Communication is actually started after
SITDR has been written.
5
No
TDREQ = 1?
Yes
6
Set the SITDR register
7
Set transmit data
Transmission and reception are carried out
Transmit SITDR from SIOFTXD
simultaneously (Even when transmission is
synchronously with SIOFSYNC
not necessary, dummy transmission must be
performed. The output of dummy transmission
can be masked by setting the pin function).
8
No
RDREQ = 1?
Yes
9
Read SIRDR register
Read receive data
10
No
Transfer complete?
Yes
Transmission and reception are carried out
simultaneously, please check the TFEMP bit
in SISTR (the transmit FIFO is empty?) and
build a waiting loop to check the
communication finished.
11
Clear the TXE bit and RXE bit in SICTR to 0
Disable transmission
End transmission
12
To be prepared for the transmission/
Clear the FSE bit in SICTR to 0
reception that is resumed later, set
the FSE bit to '0' to synchronize
the frame in this LSI.
13
Set the MSSEL bit in SISCR to 1
To be prepared for the transmission/
reception that is resumed later,
Set the BPRS to 00000 and the BRDV to 111 in SISCR
initialize inside the baud rate
generator.
Apply a pulse to bits TxRST and RxRST
in the SICTR (input 0→1→0)
Set the SISCR to set the baud rate and the master
clock source again
14
If communication is not to be
No
Change communication
mode ?
resumed (branching to No), no
further setting is needed. To return
to the same communication mode,
go back to setting of FSE at step 3
Yes
END
of this flowchart.
15
With FSE = 0, TXE = 0, and RXE = 0 held,
start setting other bits.
Go on to 'Start' of the corresponding
flowchart.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1.
Figure 16.9 (1) Transmission/Reception Operation in Master Mode (Example of Reception
and Full-Duplex Transmission by the CPU with TDMAE=0)
Rev. 6.00 Jul. 15, 2009 Page 488 of 816
REJ09B0237-0600