SH7619_09 Datasheet, PDF (202/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Setting
Setting
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
BSZ
[1:0]
A3
ROW
[1:0]
A3
COL
[1:0]
11
(32
bits)
01
01
(12 bits) (9 bits)
11
(32
bits)
01
10
(12 bits) (10 bits)
Output
Pins of Output
This Row
LSI
Address
Output
Column
Address
Pins of
SDRAM Function
Output
Pins of
This
LSI
Output
Row
Address
Output
Column
Address
Pins of
SDRAM Function
A13 A22
A12 A21
A13
L/H*¹
A11
Address
A13
A23
A10/AP Specifies A12 A22
address/
precharge
A13
L/H*¹
A11
A10/AP
Address
Specifies
address/
precharge
A11 A20
A11
A9
Address
A11
A21
A11
A9
Address
A10 A19
A10
A8
A10 A20
A10
A8
A9
A18
A9
A7
A9
A19
A9
A7
A8
A17
A8
A6
A8
A18
A8
A6
A7
A16
A7
A5
A7
A17
A7
A5
A6
A15
A6
A4
A6
A16
A6
A4
A5
A14
A5
A3
A5
A15
A5
A3
A4
A13
A4
A2
A4
A14
A4
A2
A3
A12
A3
A1
A3
A13
A3
A1
A2
A11
A2
A0
A2
A12
A2
A0
A1
A10
A1
Unused
A1
A11
A1
Unused
A0
A9
A0
A0
A10
A0
Example of memory connection
Example of memory connection
One 256-Mbit product (2 Mwords x 32 bits x 4 banks, 9-
bit column product)
One 512-Mbit product (4 Mwords x 32 bits x 4 banks, 10-
bit column product)
Two 128-Mbit products (2 Mwords x 16 bits x 4 banks, 9- Two 256-Mbit product (4 Mwords x 16 bits x 4 banks, 10-
bit column product)
bit column product)
Notes: 1. L/H is a bit used in the command specification; it is fixed low or high according to the
access mode.
2. Bank address specification
Rev. 6.00 Jul. 15, 2009 Page 162 of 816
REJ09B0237-0600