SH7619_09 Datasheet, PDF (847/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Item
Table 25.9 Bus Timing
Page Revision (See Manual for Details)
742 Added
Item
Symbol Min.
Write data hold time 2
Write data hold time 3
WAIT setup time
WAIT hold time
t_WDH2
t_WDH3
t_WTS1*
t_WTH1*
2
0
1/2 × t + 11
bcyc
1/2 × t + 10
bcyc
Note: * The AC timing specification of WAIT is as follows.
Input setup time + hold time of WAIT
= 11 [ns] + 10 [ns] = 21 [ns]
As the frequency, 47.62 [MHz]
Therefore, when the bus clock is 47.62 MHz or
more, at least either setup time or hold time
cannot be satisfied during 1-bus clock. The
following notes should be confirmed.
• When the hardware-wait function is used
synchronously
The bus clock frequency must be low enough to
satisfy the AC specification above.
• When the hardware-wait function is used
asynchronously
To ensure the setup time until the start of the
input assertion of WAIT, insert appropriate
number of the software wait after the T1 state.
Then, even if the AC specification above cannot
be satisfied, the accesses can be executed
correctly.
Rev. 6.00 Jul. 15, 2009 Page 807 of 816
REJ09B0237-0600