SH7619_09 Datasheet, PDF (189/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.5.2 Normal Space Interface
Basic Timing: For access to a normal space, this LSI uses strobe signal output in consideration of
the fact that mainly static RAM will be directly connected. When using SRAM with a byte-
selection pin, see section 7.5.6, Byte-Selection SRAM Interface. Figure 7.3 shows the basic
timings of normal space access. A no-wait normal access is completed in two cycles. The BS
signal is asserted for one cycle to indicate the start of a bus cycle.
CKIO
T1
T2
A
CSn
Read
RD/WR
RD
D
RD/WR
Write
WEn(BEn)
D
BS
Figure 7.3 Normal Space Basic Access Timing (No-Wait Access)
There is no output signal which informs external devices of the access size when reading.
Although the least significant bit of the address indicates the correct address when the access
starts, 16-bit data is always read from a 16-bit device. When writing, only the WEn (BEn) signal
for the byte to be written to is asserted.
When buffers are placed on the data bus, the RD signal should be used to control the buffers. The
RD/WR signal indicates the same state as a read cycle (driven high) when no access has been
Rev. 6.00 Jul. 15, 2009 Page 149 of 816
REJ09B0237-0600