SH7619_09 Datasheet, PDF (542/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.4.10 SPI Mode
SPI-mode operation is selected for the SIOF by the setting in SPICR.
Example of Configuration: Figure 16.21 shows an example of the configuration for SPI-mode
communications.
Master SPI
Transmit FIFO
Receive FIFO
Baud rate
generator
P/S ^MOSI
S/P ^MISO
SS0
SCK
Slave 0 SPI
SS
Figure 16.21 Example of Configuration in SPI Mode
SPI Operation: The states of operation in SPI mode are described in terms of transmission and
reception in table 16.13. In SPI mode, the data length is fixed to 8 bits and the values of the upper
8 bits of SITDR and SIRDR are the valid data for transmission and reception, respectively. Fixed
master mode can perform the full-duplex communication with the SPI slave devices continuously.
That is, 8-bit data is continuously transmitted/received, and resetting of transmit/receive operation
by the TXRST or RXRST bit with SCK = Pφ controls the respective frames.
31
24 23
0
SITDR/SIRDR
Data
The shaded part is the data which is transmitted or received.
Rev. 6.00 Jul. 15, 2009 Page 502 of 816
REJ09B0237-0600