SH7619_09 Datasheet, PDF (157/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
HIZMEM 0
R/W Hi-Z Memory Control
Specifies the pin state in standby mode for pins A25 to
A0, BS, CSn, RD/WR, WEn (BEn)/DQMxx, and RD.
0: High impedance in standby mode
1: Driven in standby mode
0
HIZCNT 0
R/W Hi-Z Control
Specifies the pin state in standby mode for the CKIO,
CKE, RAS, and CAS pins.
0: High impedance in standby mode
1: Driven in standby mode
Note: * The external pin (MD5) state for specifying endian is sampled at a power-on reset.
When big endian is specified, this bit is read as 0 and when little endian is specified,
this bit is read as 1.
7.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0, 2, 3, 4, 5B, 6B)
CSnBCR specifies the type of memory connected to each space, data-bus width of each space, and
the number of wait cycles between access cycles.
Do not access external memory other than area 0 until setting CSnBCR is completed.
Bit
31, 30
29
28
Initial
Bit Name Value R/W

All 0 R
IWW1
1
R/W
IWW0
1
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Idle Cycles between Write-Read Cycles and Write-Write
Cycles
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the area. The
write and read cycles or write and write cycles performed
consecutively are the target cycle.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
Rev. 6.00 Jul. 15, 2009 Page 117 of 816
REJ09B0237-0600