SH7619_09 Datasheet, PDF (112/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 5 Exception Handling
Power-On Reset by WDT: When TCNT of the WDT overflows while a setting is made so that a
power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-
on reset state.
If a reset caused by the signal input on the RES pin and a reset caused by a WDT overflow occur
simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0.
When the power-on reset exception handling caused by the WDT is started, the CPU operates as
follows:
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
of the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception handling vector table are set in the PC and SP, then the
program starts.
5.2.3 H-UDI Reset
The H-UDI reset is generated by issuing the H-UDI reset assert command. The CPU operation is
described below. For details, see section 21, User Debugging Interface (H-UDI).
1. The initial value (execution start address) of the program counter (PC) is fetched from the
exception handling vector table.
2. The initial value of the stack pointer (SP) is fetched from the exception handling vector table.
3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0)
in the status register (SR) are set to H'F (B'1111).
4. The values fetched from the exception handling vector table are set in PC and SP, then the
program starts.
Rev. 6.00 Jul. 15, 2009 Page 72 of 816
REJ09B0237-0600