SH7619_09 Datasheet, PDF (368/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
13.3 Register Descriptions
The DMAC has the following registers. See section 24, List of Registers, for the addresses of
these registers and the state of them in each processing status. The SAR for channel 0 is expressed
such as SAR_0.
Channel 0:
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
Channel 1:
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register _1 (CHCR_1)
Channel 2:
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
Channel 3:
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
Common:
• DMA operation register (DMAOR)
• DMA extended resource selector 0 (DMARS0)
• DMA extended resource selector 1 (DMARS1)
Rev. 6.00 Jul. 15, 2009 Page 328 of 816
REJ09B0237-0600