SH7619_09 Datasheet, PDF (12/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

3.3.4 Write-Back Buffer .............................................................................................. 59
3.3.5 Coherency of Cache and External Memory........................................................ 59
3.4 Memory-Mapped Cache ..................................................................................................... 60
3.4.1 Address Array..................................................................................................... 60
3.4.2 Data Array .......................................................................................................... 61
3.4.3 Usage Examples.................................................................................................. 63
Section 4 U Memory ........................................................................................... 65
4.1 Features............................................................................................................................... 65
4.2 Usage Notes ........................................................................................................................ 65
Section 5 Exception Handling ............................................................................. 67
5.1 Overview ............................................................................................................................ 67
5.1.1 Types of Exception Handling and Priority ......................................................... 67
5.1.2 Exception Handling Operations.......................................................................... 68
5.1.3 Exception Handling Vector Table ...................................................................... 69
5.2 Resets.................................................................................................................................. 71
5.2.1 Types of Resets................................................................................................... 71
5.2.2 Power-On Reset .................................................................................................. 71
5.2.3 H-UDI Reset ....................................................................................................... 72
5.3 Address Errors .................................................................................................................... 73
5.3.1 Address Error Sources ........................................................................................ 73
5.3.2 Address Error Exception Source......................................................................... 73
5.4 Interrupts............................................................................................................................. 74
5.4.1 Interrupt Sources................................................................................................. 74
5.4.2 Interrupt Priority ................................................................................................. 75
5.4.3 Interrupt Exception Handling ............................................................................. 75
5.5 Exceptions Triggered by Instructions ................................................................................. 76
5.5.1 Types of Exceptions Triggered by Instructions .................................................. 76
5.5.2 Trap Instructions................................................................................................. 76
5.5.3 Illegal Slot Instructions....................................................................................... 77
5.5.4 General Illegal Instructions................................................................................. 77
5.6 Cases when Exceptions are Accepted................................................................................. 78
5.7 Stack States after Exception Handling Ends....................................................................... 79
5.8 Usage Notes ........................................................................................................................ 81
5.8.1 Value of Stack Pointer (SP) ................................................................................ 81
5.8.2 Value of Vector Base Register (VBR)................................................................ 81
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling...... 81
5.8.4 Notes on Slot Illegal Instruction Exception Handling ........................................ 81
Rev. 6.00 Jul. 15, 2009 Page x of xxxviii