SH7619_09 Datasheet, PDF (563/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
17.4.5 HIF Internal Interrupt Control Register (HIFIICR)
HIFIICR is a 32-bit register used to issue interrupts from an external device connected to the HIF
to the on-chip CPU. Access to HIFIICR by an external device should be performed with HIFIICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit Bit Name Value R/W Description
31 to 8 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
IIC6
0
R/W Internal Interrupt Source
6
IIC5
0
5
IIC4
0
4
IIC3
0
3
IIC2
0
2
IIC1
0
R/W These bits specify the source for interrupts generated by
R/W ^{the IIR bit. These bits can be written to from both an}
external device and the on-chip CPU. By using these bits,
R/W _{fast execution of interrupt exception handling is possible.}
R/W ^{These bits are completely under software control, and}
R/W ^{their values have no effect on the operation of this LSI.}
1
IIC0
0
R/W
0
IIR
0
R/W Internal Interrupt Request
While this bit is 1, an interrupt request (HIFI) is issued to
the on-chip CPU.
17.4.6 HIF External Interrupt Control Register (HIFEICR)
HIFEICR is a 32-bit register used to issue interrupts to an external device connected to the HIF
from this LSI. Access to HIFEICR by an external device should be performed with HIFEICR
specified by bits REG5 to REG0 in HIFIDX and the HIFRS pin low.
Initial
Bit Bit Name Value R/W Description
31 to 8 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 6.00 Jul. 15, 2009 Page 523 of 816
REJ09B0237-0600