SH7619_09 Datasheet, PDF (851/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

M
MAC interface ........................................ 657
Magic packet detection ........................... 261
Management signals ............................... 667
Manchester decoding .............................. 656
Manchester encoding .............................. 655
Memory data formats................................ 28
Memory-mapped cache ............................ 60
MII.......................................................... 657
MII frame timing .................................... 256
MII signals.............................................. 666
Miscellaneous functions ......................... 661
Module standby mode............................. 232
Multi-buffer frame
transmit/receive processing .................... 304
multiplexed pin ....................................... 543
N
NMI interrupt............................................ 97
Normal space interface ........................... 149
NRZI and MLT-3 decoding.................... 652
NRZI and MLT3 encoding ..................... 650
O
On-chip peripheral module interrupts....... 99
On-chip peripheral module
request mode........................................... 344
Operation by IPG setting ........................ 262
Operation mode ...................................... 667
P
Parallel detection .................................... 660
PCMCIA interface .................................. 191
PHY (on-chip PHY module)................... 631
PHY address ........................................... 667
PHY interface (PHY-IF)......................... 683
PHY management control....................... 635
Pin assignments........................................... 8
Pin function controller (PFC).................. 543
Pin functions ............................................... 9
Power-down modes......................... 223, 662
Power-on reset .......................................... 71
Power-on sequence ................................. 184
R
Read access ............................................... 58
Receive data valid signal......................... 653
Receive descriptor 0 (RD0)..................... 297
Receive descriptor 1 (RD1)..................... 300
Receive descriptor 2 (RD2)..................... 300
Receiver errors ........................................ 654
Receiving serial data
(asynchronous mode) .............................. 423
Receiving serial data
(synchronous mode)................................ 432
Refreshing............................................... 181
Register data format.................................. 28
Registers
APR............................. 251, 699, 719, 728
BAMRA...................... 596, 699, 720, 728
BAMRB ...................... 598, 699, 720, 728
BARA ......................... 595, 699, 720, 728
BARB.......................... 597, 699, 720, 728
BBRA.......................... 596, 699, 721, 728
BBRB.......................... 599, 699, 720, 728
BDMRB ...................... 599, 699, 719, 728
BDRB.......................... 598, 699, 719, 728
BETR .......................... 604, 699, 720, 728
BRCR.......................... 601, 699, 719, 728
BRDR.......................... 605, 699, 721, 728
BRSR .......................... 604, 699, 720, 728
CCR1 ............................ 56, 699, 721, 728
CDCR.......................... 248, 698, 717, 727
CEFCR........................ 249, 698, 718, 728
CHCR.................................................. 330
CHCR_0.............................. 692, 700, 722
Rev. 6.00 Jul. 15, 2009 Page 811 of 816
REJ09B0237-0600