SH7619_09 Datasheet, PDF (633/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
Section 20 User Break Controller (UBC)
The user break controller (UBC) provides functions that simplify program debugging. These
functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug
programs without using an in-circuit emulator. Break conditions that can be set in the UBC are
instruction fetch or data read/write access, data size, data contents, address value, and stop timing
in the case of instruction fetch.
20.1 Features
The UBC has the following features:
• The following break comparison conditions can be set.
Number of break channels: two channels (channels A and B)
User break can be requested as either the independent or sequential condition on channels A
and B (sequential break: when channel A and channel B match with break conditions in the
different bus cycles in that order, a break condition is satisfied).
 Address (Compares addresses 32 bits):
Comparison bits are maskable in 1-bit units; user can mask addresses at lower 12 bits (4-k
page), lower 10 bits (1-k page), or any size of page, etc.
One of the two address buses (L-bus address (LAB) and I-bus address (IAB)) can be
selected.
 Data (only on channel B, 32-bit maskable)
One of the two data buses (logic data bus (LDB) and internal data bus (IDB)) can be
selected.
 Bus cycle: Instruction fetch or data access
 Read/write
 Operand size: Byte, word, or longword
• User break interrupt is generated upon satisfying break conditions. A user-designed user-break
condition interrupt exception processing routine can be run.
• In an instruction fetch cycle, it can be selected that a break is set before or after an instruction
is executed.
• Maximum repeat times for the break condition (only for channel B): 2¹² – 1 times.
• Four pairs of branch source/destination buffers.
Rev. 6.00 Jul. 15, 2009 Page 593 of 816
REJ09B0237-0600