SH7619_09 Datasheet, PDF (530/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Reception in Master Mode: Figure 16.10 shows an example of settings and operation for master
mode reception.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SIRDAR, SICDAR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
3
Start SIOFSCK output
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit/receive
data, slot position for control data,
and FIFO request threshold value
Set operation start for baud rate
generator
Output serial clock
4
Set the FSE and RXE bits
in SICTR to 1
Set the start for frame synchronous
signal output and enable
reception
Output frame
signal
synchronous
Store SIOFRXD receive data in SIRDR
5
synchronously with SIOFSYNC
Issue receive transfer
request according to the
receive FIFO threshold
value
6
RDREQ = 1? ^No
Yes
Reception
7
Read SIRDR
Read receive data
Transfer
No
ended?
8
Yes
Clear the RXE bit in SICTR to 0
End
Set to disable reception
End reception
Figure 16.10 Example of Receive Operation in Master Mode
Rev. 6.00 Jul. 15, 2009 Page 490 of 816
REJ09B0237-0600