SH7619_09 Datasheet, PDF (709/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(3) Software Reset of the PHY
The software reset of the on-chip PHY of this LSI has a defect in characteristics, which can
prevent correct resetting of the PHY in some cases. Because of this, the PHY should be reset by a
module reset, which is generated by setting the PHYIFCR register (in the PHY-IF module).
Note: 1. Software reset refers to the reset which is executed by bit 15 of register 0 (basic
control) described in section 22.4.2, SMI Register Mapping.
2. Module reset refers to the reset which is executed by bit 14 of PHYIFCR (PHY-IF
control register) described in section 23.2, Register Descriptions, in section 23, PHY
Interface (PHY-IF).
(4) Waveform Adjustment
The Ethernet PHY module of this LSI has test registers for adjustment of differential output
waveforms. Using these test registers in their initial values produces no problem, but their
specifications are shown below to facilitate printed circuit board design by the customer.
(a) Adjustment of Tx100 Waveform Output
The on-chip PHY module of this LSI has the following adjustment registers as SIM registers,
which allow waveform adjustment in the Tx100 operation. These registers have been designed so
that they are not accidentally written. To change their values, follow the example procedure shown
in "How to Use" that is described later.
• Register 20: Register for changing modes
• Register 23: Register for waveform adjustment
(The register numbers are decimal)
• Meanings of the value written to register 23
Initial
Bit
Bit Name Value R/W
Description
15

1
RO
Reserved
The write value should always be 1.
14 to 9 
0
RO
Reserved
The write value should always be 0.
Rev. 6.00 Jul. 15, 2009 Page 669 of 816
REJ09B0237-0600