SH7619_09 Datasheet, PDF (812/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 25 Electrical Characteristics
SCK
TxD
(data transmission)
RxD
(data reception)
RTS
CTS
t_Scyc
t_TXD
t_RTSD
t_RXS t_RXH
t_CTSS t_CTSH
Figure 25.40 SCI Input/Output Timing in Clocked Synchronous Mode
25.4.9 SIOF Module Signal Timing
Table 25.12 SCIF Timing
Conditions: V_CCQ = 3.0 V to 3.6 V, V_CC = 1.71 V to 1.89 V; for Ta, see the operating
temperatures given in appendix B, Product Code Lineup.
Item
SIOMCLK clock input cycle time
SIOMCLK input high pulse width
SIOMCLK input low pulse width
SCK_SIO clock cycle time
Symbol
t_Mcyc
t_MWH
t_MWL
t_SIcyc
Min.
Max.
32

0.4 × t_Mcyc 
0.4 × t_Mcyc 
2 × t_pcyc* 
SCK_SIO output high pulse width t
SWHO
SCK_SIO output low pulse width t
SWLO
SIOFSYNC output delay time
t
FSD
SCK_SIO input high pulse width t_SWHI
SCK_SIO input low pulse width
t_SWLI
SIOFSYNC input set-up time
t_FSS
SIOFSYNC input hold time
t_FSH
0.4 × t 
SIcyc
0.4 × t 
SIcyc

20
0.4 × t_SIcyc 
0.4 × t_SIcyc 
20

20

Unit Reference Figures
ns Figure 25.41
Figures 25.42 to
25.46
Figures 25.42 to
25.45
Figure 25.46
Rev. 6.00 Jul. 15, 2009 Page 772 of 816
REJ09B0237-0600