SH7619_09 Datasheet, PDF (547/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
No.
Time chart
Start
1
Set SISCR, SIFCTR, and SPICR.
SIOF Setting
SIOF Operation
Set the serial clock and threshold values for FIFO.
[Note] In SPI mode, registers SIMDR, SITDAR, SIRDAR,
and SICDAR should be set to their initial values.
2
Set the SCKE bit in SICTR to 1.
Start baud rate generator operation.
[Note] Serial clock will not be output form the pin until
communication is actually started.
3
Set the FSE bit in SICTR to 1.
Set the TXE bit in SICTR to 1.*
Initialize the frame in the SIOF (ie, initialize the
state of signal SS0), and enable transmission.
[Note] Communication is actually started after SITDR
has been written.
4
TDREQ=1?
No
Yes
5
Set the SITDR register.
Set the data for transmission.
6
Synchronously to SS0, output the
contents of SITDR from MOSI.
Executes transmission.
No
Check SISTR.TFEMP (transmit FIFO empty) and
7
Transfer complete?
ensure completion of communication by using a
Yes
wait loop or other means.
8
Clear the TXE bit in SICTR to 0.
Disable transmission.
Transmission ends.
To be prepared for the transmission/reception that
9
Clear the FSE bit in SICTR to 0.
is resumed later, set FSE = 0 to synchronize
the frame in this LSI.
Set BPRS = 00000 and BRDV = 111
in the SISCR register.
10
Apply a pulse to bit TxRST in the
SICTR register (0->1->0 input).
To be prepared for the transmission/reception that
is resumed later, initialize inside the baud rate
generator.
Set the SISCR register to set
the baud rate again.
If communication is not to be resumed
11
Change
No
(branching to No), no further setting is needed.
communication mode?
To return to the same communication mode,
Yes
End go back to setting of FSE at step 3 of this flowchart.
12
With FSE=0, TXE=0, and RXE=0
held, start setting other bits.
Go on to 'Start' of the corresponding flowchart.
Note: * For the case when interrupt generation on transmit FIFO underflow is enabled, set the TXE bit to 1 after setting data for transmission at step No.5.
Figure 16.25 SPI Transmission Operation (Example of Half-Duplex Transmission by the
CPU with TDMAE = 0)
Rev. 6.00 Jul. 15, 2009 Page 507 of 816
REJ09B0237-0600