SH7619_09 Datasheet, PDF (152/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
7.3.2 Shadow Area
Areas 0, 3, 4, 5B, and 6B are divided by decoding physical address bits A28 to A25, which
correspond to areas 000 to 111. Address bits 31 to 29 are ignored. This means that the range of
area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space
is the address space in P1 to P3 areas obtained by adding to it H'20000000 × n (n = 1 to 6).
The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7
shadow spaces are reserved, so do not use it.
Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is allocated to internal register
addresses. Therefore, area P4 does not become shadow space.
H'00000000
H'20000000
P0
H'40000000
H'60000000
H'80000000
P1
H'A0000000
P2
H'C0000000
P3
H'E0000000
P4
Area 0 (CS0)
Area 1 (reserved)
Area 2 (reserved)
Area 3 (CS3)
Area 4 (CS4)
Area 5A (reserved)
Area 5B (CS5B)
Area 6A (reserved)
Area 6B (CS6B)
Area 7 (reserved)
Physical address space
Address Space
Figure 7.2 Address Space
7.3.3 Address Map
The external address space has a capacity of 256 Mbytes and is divided into five areas. Types of
memory to be connected and the data bus width are specified for individual areas. The address
map for the external address space is shown in table 7.2.
Rev. 6.00 Jul. 15, 2009 Page 112 of 816
REJ09B0237-0600