SH7619_09 Datasheet, PDF (573/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
HIFCS
HIFRS
HIFRD
HIFWR
HIFD15 to HIFD00
0016 AHAL 000A 0088 0018 D0D1 D2D3 D4D5 D6D7 D8D9 DADB DCDD
HIFADR setting HIFMCR setting HIFDATA
[15:8] = AH Consecutive read selection
[7:0] = AL
Auto-increment
Consecutive data reading
Figure 17.7 Consecutive Data Reading from HIFRAM
17.8 External DMAC Interface
Figures 17.8 to 17.11 show the HIFDREQ output timing. The start of the HIFDREQ assert
synchronizes with the DTRG bit in HIFDTR being set to 1. The HIFDREQ negate timing and
assert level are determined by the DMD and DPOL bits in HIFSCR, respectively.
When the external DMAC is specified to detect low level of the HIFDREQ signal, set DMD = 0
and DPOL = 0. After writing 1 to the DTRG bit, the HIFDREQ signal remains low until low level
is detected for both the HIFCS and HIFRS signals.
In this case, when the HIFDREQ signal is used, make sure that the setup time (HIFCS assertion to
HIFRS settling) and the hold time (HIFRS hold to HIFCS negate) are satisfied. If t_HIFAS and t_HIFAH
stipulated in section 25.4.11, HIF Timing, are not satisfied, the HIFDREQ signal may be negated
unintentionally.
Rev. 6.00 Jul. 15, 2009 Page 533 of 816
REJ09B0237-0600