SH7619_09 Datasheet, PDF (552/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 17 Host Interface (HIF)
Figure 17.1 shows a block diagram of the HIF.
HIF
HIFD15 to HIFD00
Select
HIFRAM
HIFRAM
HIFCS
HIFRS
HIFWR
HIFRD
HIFMD
HIFINT
HIFDREQ
HIFRDY
HIFEBL
Control circuit
HIFI
HIFBI
[Legend]
HIFIDX:
HIFGSR:
HIFSCR:
HIFMCR:
HIFIICR:
HIFEICR:
HIF index register
HIF general status register
HIF status/control register
HIF memory control register
HIF internal interrupt control register
HIF external interrupt control register
HIFADR:
HIFDATA:
HIFBCR:
HIFDTR:
HIFBICR:
HIFI:
HIFIB:
HIF address register
HIF data register
HIF boot control register
HIFDREQ trigger register
HIF bank interrupt control register
HIF interrupt (internal interrupt)
HIF bank interrupt (internal interrupt)
Figure 17.1 Block Diagram of HIF
Rev. 6.00 Jul. 15, 2009 Page 512 of 816
REJ09B0237-0600