SH7619_09 Datasheet, PDF (277/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.3 Register Description
The EtherC has the following registers. For details on addresses and access sizes of registers, see
section 24, List of Registers.
MAC Layer Interface Control Registers:
• EtherC mode register (ECMR)
• EtherC status register (ECSR)
• EtherC interrupt permission register (ECSIPR)
• PHY interface register (PIR)
• MAC address high register (MAHR)
• MAC address low register (MALR)
• Receive frame length register (RFLR)
• PHY status register (PSR)
• Transmit retry over counter register (TROCR)
• Delayed collision detect counter register (CDCR)
• Lost carrier counter register (LCCR)
• Carrier not detect counter register (CNDCR)
• CRC error frame counter register (CEFCR)
• Frame receive error counter register (FRECR)
• Too-short frame receive counter register (TSFRCR)
• Too-long frame receive counter register (TLFRCR)
• Residual-bit frame counter register (RFCR)
• Multicast address frame counter register (MAFCR)
• IPG register (IPGR)
• Automatic PAUSE frame set register (APR)
• Manual PAUSE frame set register (MPR)
• PAUSE frame retransfer count set register (TPAUSER)
Rev. 6.00 Jul. 15, 2009 Page 237 of 816
REJ09B0237-0600