SH7619_09 Datasheet, PDF (645/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
Initial
Bit
Bit Name Value
30 to 28 —
All 0
27 to 0 BSA27 to Undefined
BSA0
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Source Address
Store bits 27 to 0 of the branch source address.
20.2.12 Branch Destination Register (BRDR)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset. Other bits are not initialized by a power-on reset. The four BRDR registers have
a queue structure and a stored register is shifted at every branch.
Initial
Bit
Bit Name Value
R/W Description
31
DVF
0
R
BRDR Valid Flag
Indicates whether or not the branch source address is
stored. When a branch is made, this flag is set to 1.
This flag is cleared to 0 by one of the following
conditions: when this flag is read from this register,
when PC trace is enabled, and when a power-on reset
is generated.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
30 to 28 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
27 to 0 BDA27 to Undefined R
BDA0
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
Rev. 6.00 Jul. 15, 2009 Page 605 of 816
REJ09B0237-0600