SH7619_09 Datasheet, PDF (724/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
Figure 23.1 shows the block diagram of PHY-IF.
Internal bus
PFY-IF register
Reset
Module reset
(co_resetb)
CPG
Internal
clock
External clock input
Selection
(clksel)
Internal PHY
Reset
PHY clock
Port (EtherC inputs)
PFC
EtherC
function selected
LED signals
MII signals
Input pins
MII signals
Ether C
Ports
TXP/M,
RXP/M etc.
Input/output
pins
PFC
EtherC
function
selected
Output pins
[Legend]
PHYIFCR: PHY-IF control register
PHYIFSMIR2: PHY-IF SMI register 2
PHYIFSMIR3: PHY-IF SMI register 3
PHYIFADDRR: PHY-IF address register
PHYIFSR:
PHY-IF status register
Figure 23.1 Block Diagram of PHY-IF
Rev. 6.00 Jul. 15, 2009 Page 684 of 816
REJ09B0237-0600