SH7619_09 Datasheet, PDF (694/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(8) Receiver Errors
During a frame, unexpected code-groups are considered receive errors. Expected code groups are
the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the
CO_RX_ER signal is asserted and arbitrary data is driven onto the CO_MII_RXD lines. Should an
error be detected during the time that the /J/K/ delimiter is being decoded (bad SSD error),
CO_RX_ER is asserted true and the value '1110' is driven onto the CO_MII_RXD lines. Note that
the Valid Data signal is not yet asserted when the bad SSD error occurs.
(9) 100M Receive Data across the MII
The 4-bit data nibbles are sent to the MII block. These data nibbles are clocked to the controller at
a rate of 25MHz. The controller samples the data on the rising edge of CO_RX_CLK.
CO_RX_CLK is the 25MHz output clock for the MII bus. It is recovered from the received data to
clock the CO_MII_RXD bus. If there is no received signal, it is derived from the system reference
clock (CO_CLKIN).
When tracking the received data, CO_RX_CLK has a maximum jitter of 0.8ns (provided that the
jitter of the input clock, CO_CLKIN, is below 100ps).
22.7 10Base-T Transmit
Data to be transmitted comes from the MAC layer controller. The 10Base-T transmitter receives
4-bit nibbles from the MII at a rate of 2.5MHz and converts them to a 10Mbps serial data stream.
The data stream is then Manchester-encoded and sent to the analog transmitter which drives a
signal onto the twisted pair via the external magnetics.
The 10M transmitter uses the following blocks:
• MII (digital)
• TX 10M (digital)
• 10M Transmitter (analog)
• 10M PLL (analog)
Rev. 6.00 Jul. 15, 2009 Page 654 of 816
REJ09B0237-0600