SH7619_09 Datasheet, PDF (299/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
MII Register Access Procedure: The program accesses MII registers via the PHY interface
register (PIR). Access is implemented by a combination of 1-bit-unit data write, 1-bit-unit data
read, bus release, and independent bus release. Figure 11.9 shows the MII register access timing.
The timing will differ depending on the PHY type.
(1) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 0
(2) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 1
MDC
MDO
(1) (2)
(3)
1-bit data write timing
relationship
(3) Write to PHY interface
register
MMD = 1
MDO = write data
MDC = 0
Figure 11.6 (1) 1-Bit Data Write Flowchart
Rev. 6.00 Jul. 15, 2009 Page 259 of 816
REJ09B0237-0600