SH7619_09 Datasheet, PDF (636/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
20.2.2 Break Address Mask Register A (BAMRA)
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
Bit
31 to 0
Bit Name
Initial
Value R/W
BAMA31 to All 0 R/W
BAMA 0
Description
Break Address Mask A
Specify bits masked in the channel A break address bits
specified by BARA (BAA31 to BAA0).
0: Break address bit BAAn of channel A is included in
the break condition
1: Break address bit BAAn of channel A is masked and
is not included in the break condition
Note: n = 31 to 0
20.2.3 Break Bus Cycle Register A (BBRA)
Break bus cycle register A (BBRA) is a 16-bit readable/writable register, which specifies (1) L bus
cycle or I bus cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in
the break conditions of channel A.
Initial
Bit
Bit Name Value R/W
15 to 8 —
All 0 R
7
CDA1 0
R/W
6
CDA0 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle of the
channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
Rev. 6.00 Jul. 15, 2009 Page 596 of 816
REJ09B0237-0600