SH7619_09 Datasheet, PDF (721/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
(6) Clock Layout
In addition to the clock input for the CPU, an external clock for the PHY (CKPHY) can also be
input to this LSI.
Analog power supply and analog signals should be placed far away from the oscillator, resonator,
and digital devices that produce much noise. Clock signal lines should be wired in a layer higher
than the ground layer (the top layer (component side) in this example). In addition, clock traces
should be kept as far away from other traces as possible. The minimum spacing is three times of
the trace width.
Rev. 6.00 Jul. 15, 2009 Page 681 of 816
REJ09B0237-0600