SH7619_09 Datasheet, PDF (729/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 23 PHY Interface (PHY-IF)
23.3 PHY-IF Operation
PHY-IF is basically for initializing the on-chop PHY module.
Following the procedures described in the following sections, please set up the on-chip PHY
module with the MII interface like as for the external PHY LSI. The PHY module itself goes to
power down mode with the initial values of co_st_mode of PHYIFCR after power-on-reset of the
whole LSI at power-up.
23.3.1 The Procedures of Setting Up the On-Chip PHY
Please set up with below procedures.
1. Release of module stop
First of all, release the module stop (MSTP20 of STBCR4), if PHY-IF is in module stop mode.
2. Power Up Reset
Check the release of power up reset mode, shown in the co_pwruprst-bit of PHYIFSR with
value "0".
3. Activation of the on-chip PHY module
To activate the on-chip PHY module, set the pin function registers of Port C as something but
EtherC function, that is, I/O ports and LED outputs of the on-chip PHY.
• PCCRH2 = H'0000
• PCCRL1 = H'0000
• PCCRL2 = H'FF00
In this case, the LNKSTA input pin of the EtherC is deselected. As the link output of the on-
chip PHY and link input of the EtherC are connected in this LSI, the link signal change
interrupt can be generated in the same way as the external PHY LSI is used.
4. Set up of the clock
In the case of utilizing the internal clock from CPG, you have to set up the MCLKCR during
the reset period of the on-chip PHY. Set the input clock of the PHY module as 25 MHz by
adjusting the FRQCR and MCLKCR.
Do this set up before module reset of the on-chip PHY.
Rev. 6.00 Jul. 15, 2009 Page 689 of 816
REJ09B0237-0600