SH7619_09 Datasheet, PDF (83/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
• Data Transfer Instructions
Instruction
Operation
Code
Execution
Cycles
T Bit
MOV #imm,Rn
imm → Sign extension 1110nnnniiiiiiii 1

→ Rn
MOV.W @(disp,PC),Rn (disp × 2 + PC) → Sign 1001nnnndddddddd 1

extension → Rn
MOV.L @(disp,PC),Rn (disp × 4 + PC) → Rn 1101nnnndddddddd 1

MOV Rm,Rn
Rm → Rn
0110nnnnmmmm0011 1

MOV.B Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0000 1

MOV.W Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0001 1

MOV.L Rm,@Rn
Rm → (Rn)
0010nnnnmmmm0010 1

MOV.B @Rm,Rn
(Rm) → Sign extension 0110nnnnmmmm0000 1

→ Rn
MOV.W @Rm,Rn
(Rm) → Sign extension 0110nnnnmmmm0001 1

→ Rn
MOV.L @Rm,Rn
(Rm) → Rn
0110nnnnmmmm0010 1

MOV.B Rm,@–Rn
Rn–1 → Rn, Rm → (Rn) 0010nnnnmmmm0100 1

MOV.W Rm,@–Rn
Rn–2 → Rn, Rm → (Rn) 0010nnnnmmmm0101 1

MOV.L Rm,@–Rn
Rn–4 → Rn, Rm → (Rn) 0010nnnnmmmm0110 1

MOV.B @Rm+,Rn
(Rm) → Sign extension 0110nnnnmmmm0100 1

→ Rn, Rm + 1 → Rm
MOV.W @Rm+,Rn
(Rm) → Sign extension 0110nnnnmmmm0101 1

→ Rn, Rm + 2 → Rm
MOV.L @Rm+,Rn
(Rm) → Rn,Rm + 4 → Rm 0110nnnnmmmm0110 1

MOV.B R0,@(disp,Rn) R0 → (disp + Rn)
10000000nnnndddd 1

MOV.W R0,@(disp,Rn) R0 → (disp × 2 + Rn)
10000001nnnndddd 1

MOV.L Rm,@(disp,Rn) Rm → (disp × 4 + Rn) 0001nnnnmmmmdddd 1

MOV.B @(disp,Rm),R0 (disp + Rm) → Sign
10000100mmmmdddd 1

extension → R0
MOV.W @(disp,Rm),R0 (disp × 2 + Rm) → Sign 10000101mmmmdddd 1

extension → R0
MOV.L @(disp,Rm),Rn (disp × 4 + Rm) → Rn 0101nnnnmmmmdddd 1

MOV.B Rm,@(R0,Rn) Rm → (R0 + Rn)
0000nnnnmmmm0100 1

MOV.W Rm,@(R0,Rn) Rm → (R0 + Rn)
0000nnnnmmmm0101 1

Rev. 6.00 Jul. 15, 2009 Page 43 of 816
REJ09B0237-0600