SH7619_09 Datasheet, PDF (19/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

16.3.8 Interrupt Enable Register (SIIER)..................................................................... 465
16.3.9 FIFO Control Register (SIFCTR) ..................................................................... 467
16.3.10 Clock Select Register (SISCR) ......................................................................... 469
16.3.11 Transmit Data Assign Register (SITDAR) ....................................................... 470
16.3.12 Receive Data Assign Register (SIRDAR)......................................................... 472
16.3.13 Control Data Assign Register (SICDAR) ......................................................... 473
16.3.14 SPI Control Register (SPICR) .......................................................................... 474
16.4 Operation .......................................................................................................................... 477
16.4.1 Serial Clocks ..................................................................................................... 477
16.4.2 Serial Timing .................................................................................................... 478
16.4.3 Transfer Data Format........................................................................................ 479
16.4.4 Register Allocation of Transfer Data ................................................................ 481
16.4.5 Control Data Interface....................................................................................... 483
16.4.6 FIFO.................................................................................................................. 485
16.4.7 Transmit and Receive Procedures..................................................................... 487
16.4.8 Interrupts........................................................................................................... 494
16.4.9 Transmit and Receive Timing........................................................................... 496
16.4.10 SPI Mode .......................................................................................................... 502
Section 17 Host Interface (HIF).........................................................................511
17.1 Features............................................................................................................................. 511
17.2 Input/Output Pins.............................................................................................................. 513
17.3 Parallel Access.................................................................................................................. 514
17.3.1 Operation .......................................................................................................... 514
17.3.2 Connection Method........................................................................................... 514
17.4 Register Descriptions........................................................................................................ 515
17.4.1 HIF Index Register (HIFIDX)........................................................................... 515
17.4.2 HIF General Status Register (HIFGSR)............................................................ 518
17.4.3 HIF Status/Control Register (HIFSCR) ............................................................ 518
17.4.4 HIF Memory Control Register (HIFMCR) ....................................................... 521
17.4.5 HIF Internal Interrupt Control Register (HIFIICR) .......................................... 523
17.4.6 HIF External Interrupt Control Register (HIFEICR) ........................................ 523
17.4.7 HIF Address Register (HIFADR) ..................................................................... 524
17.4.8 HIF Data Register (HIFDATA) ........................................................................ 525
17.4.9 HIF Boot Control Register (HIFBCR).............................................................. 525
17.4.10 HIFDREQ Trigger Register (HIFDTR) ............................................................ 526
17.4.11 HIF Bank Interrupt Control Register (HIFBICR) ............................................. 527
17.5 Memory Map .................................................................................................................... 529
17.6 Interface (Basic)................................................................................................................ 530
17.7 Interface (Details) ............................................................................................................. 531
Rev. 6.00 Jul. 15, 2009 Page xvii of xxxviii