SH7619_09 Datasheet, PDF (84/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 2 CPU
Instruction
Operation
Code
Execution
Cycles
T Bit
MOV.L Rm,@(R0,Rn) Rm → (R0 + Rn)
0000nnnnmmmm0110 1

MOV.B @(R0,Rm),Rn (R0 + Rm) → Sign
0000nnnnmmmm1100 1

extension → Rn
MOV.W @(R0,Rm),Rn (R0 + Rm) → Sign
0000nnnnmmmm1101 1

extension → Rn
MOV.L @(R0,Rm),Rn (R0 + Rm) → Rn
0000nnnnmmmm1110 1

MOV.B R0,@(disp,GBR) R0 → (disp + GBR)
11000000dddddddd 1

MOV.W R0,@(disp,GBR) R0 → (disp × 2 + GBR) 11000001dddddddd 1

MOV.L R0,@(disp,GBR) R0 → (disp × 4 + GBR) 11000010dddddddd 1

MOV.B @(disp,GBR),R0 (disp + GBR) → Sign
11000100dddddddd 1

extension → R0
MOV.W @(disp,GBR),R0 (disp × 2 + GBR) →
11000101dddddddd 1

Sign extension → R0
MOV.L @(disp,GBR),R0 (disp × 4 + GBR) → R0 11000110dddddddd 1

MOVA @(disp,PC),R0 disp × 4 + PC → R0
11000111dddddddd 1

MOVT Rn
T → Rn
0000nnnn00101001 1

SWAP.B Rm,Rn
Rm → Swap lowest two 0110nnnnmmmm1000 1

bytes → Rn
SWAP.W Rm,Rn
Rm → Swap two
0110nnnnmmmm1001 1

consecutive words → Rn
XTRCT Rm,Rn
Rm: Middle 32 bits of
0010nnnnmmmm1101 1

Rn → Rn
Rev. 6.00 Jul. 15, 2009 Page 44 of 816
REJ09B0237-0600