SH7619_09 Datasheet, PDF (293/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 11 Ethernet Controller (EtherC)
11.4 Operation
The overview of the Ethernet controller (EtherC) are shown below. The EtherC transmits and
receives PAUSE frames conforming to the Ethernet/IEEE802.3x frames.
11.4.1 Transmission
The EtherC transmitter assembles the transmit data on the frame and outputs to MII when there is
a transmit request from the E-DMAC. The data transmitted via the MII is transmitted to the lines
by PHY-LSI. Figure 11.3 shows the state transition of the EtherC transmitter.
Rev. 6.00 Jul. 15, 2009 Page 253 of 816
REJ09B0237-0600