SH7619_09 Datasheet, PDF (849/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Index
Numerics
100Base-TX receive ............................... 651
100Base-TX transmit.............................. 648
100M phase lock loop (PLL) .................. 651
100M receive data across the MII........... 654
100M receive input................................. 651
100M transmit data across the MII ......... 648
100M transmit driver .............................. 650
10Base-T receive .................................... 656
10Base-T transmit................................... 654
10M receive data across the MII............. 656
10M receive input and squelch ............... 656
10M transmit data across the MII ........... 655
10M transmit drivers............................... 655
4B/5B encoding ...................................... 648
5B/4B decoding ...................................... 653
A
Access wait control................................. 154
Accessing MII registers .......................... 258
Address array............................................ 60
Address error exception handling ............. 73
Address error sources ............................... 73
Address multiplexing.............................. 159
Addressing modes..................................... 32
Alignment ............................................... 653
Arithmetic operation instructions ............. 45
Asynchronous mode ............................... 414
Auto-negotiation..................................... 658
Auto-negotiation disabling ..................... 660
Auto-refreshing....................................... 181
Auto-request mode ................................. 343
B
Bank active ............................................. 174
Basic timing ............................................ 149
Basic timing for I/O card interface.......... 195
Basic timing for
memory card interface ............................ 193
Baud rate generator ................................. 477
Bit rate..................................................... 398
Boundary scan......................................... 629
Branch instructions ................................... 48
Burst mode.............................................. 354
Burst read................................................ 168
Burst write............................................... 172
Bus state controller (BSC) ...................... 107
Byte-selection SRAM interface .............. 186
C
Cache ........................................................ 53
Cache structure.......................................... 53
Carrier sense ........................................... 661
Cases when exceptions are accepted......... 78
Changing clock operating mode.............. 211
Changing division ratio........................... 211
Changing frequency ................................ 210
Changing multiplication ratio ................. 210
Clock operating modes ........................... 204
Clock pulse generator (CPG) .................. 201
Coherency of cache and
external memory ....................................... 59
Collision detect ....................................... 661
Compare match timer (CMT) ................. 367
Connection to PHY-LSI.......................... 263
Control registers........................................ 25
CPU........................................................... 23
Cycle-steal mode..................................... 352
Rev. 6.00 Jul. 15, 2009 Page 809 of 816
REJ09B0237-0600