SH7619_09 Datasheet, PDF (147/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Section 7 Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
7.1 Features
The BSC has the following features.
• External address space
 A maximum 32 or 64 Mbytes for each of the areas, CS0, CS3, CS4, CS5B, and CS6B,
totally 256 Mbytes (divided into five areas)
 A maximum 64 Mbytes for each of the six areas, CS0, CS3, CS4, CS5, and CS6, totally
320 Mbytes (divided into five areas)
 Can specify the normal space interface, byte-selection SRAM, SDRAM, PCMCIA for each
address space
 Can select the data bus width (8, 16, or 32 bits) for each address space. (The CS0 data bus
width can only be selected from 8 or 16 bits.)
 Can control the insertion of wait cycles for each address space
 Can control the insertion of wait cycles for each read access and write access
 Can control the insertion of idle cycles in the consecutive access for five cases
independently: read-write (in same space/different space), read-read (in same
space/different space), or the first cycle is a write access
• Normal space interface
 Supports the interface that can directly connect to the SRAM
• SDRAM interface
 Can connect directly to SDRAM in area 3
 Multiplex output for row address/column address
 Efficient access by single read/single write
 High-speed access by bank-active mode
 Supports auto-refreshing and self-refreshing
Rev. 6.00 Jul. 15, 2009 Page 107 of 816
REJ09B0237-0600