SH7619_09 Datasheet, PDF (95/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
3.1.2 Divided Areas and Cache
A 4-G byte address space is divided into five areas with the architecture of this LSI. The cache
access methods can be specified for each area. Table 3.2 lists the correspondence between the
divided areas and cache.
Table 3.2 Correspondence between Divided Areas and Cache
Address
Area
H'00000000 to H'7FFFFFFF P0
H'80000000 to H'9FFFFFFF P1
H'A0000000 to H'BFFFFFFF P2
H'C0000000 to H'DFFFFFFF P3
H'E0000000 to H'FFFFFFFF P4
Cacheable
Cache Operating
Control
Cacheable
WT bit in CCR1
Cacheable
CB bit in CCR1
Non cacheable

Cacheable
WT bit in CCR1
Non cacheable (internal I/O) 
Rev. 6.00 Jul. 15, 2009 Page 55 of 816
REJ09B0237-0600