SH7619_09 Datasheet, PDF (637/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 20 User Break Controller (UBC)
Initial
Bit
Bit Name Value R/W Description
5
IDA1
0
R/W Instruction Fetch/Data Access Select A
4
IDA0
0
R/W Select the instruction fetch cycle or data access cycle as
the bus cycle of the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the instruction fetch cycle
10: The break condition is the data access cycle
11: The break condition is the instruction fetch cycle or data
access cycle
3
RWA1 0
R/W Read/Write Select A
2
RWA0 0
R/W Select the read cycle or write cycle as the bus cycle of the
channel A break condition.
00: Condition comparison is not performed
01: The break condition is the read cycle
10: The break condition is the write cycle
11: The break condition is the read cycle or write cycle
1
SZA1 0
R/W Operand Size Select A
0
SZA0 0
R/W Select the operand size of the bus cycle for the channel A
break condition.
00: The break condition does not include operand size
01: The break condition is byte access
10: The break condition is word access
11: The break condition is longword access
20.2.4 Break Address Register B (BARB)
BARB is a 32-bit readable/writable register. BARB specifies the address used for a break
condition in channel B.
Initial
Bit
Bit Name Value R/W
31 to 0 BAB31 to All 0 R/W
BAB 0
Description
Break Address B
Store an address of LAB or IAB which specifies a break
condition in channel B.
Rev. 6.00 Jul. 15, 2009 Page 597 of 816
REJ09B0237-0600