SH7619_09 Datasheet, PDF (32/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Figure 25.14 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle, One Asynchronous
External Wait Cycle, CSnWCR.BAS = 0 (UB-/LB-Controlled Write Cycle) ...... 747
Figure 25.15 Byte Control SRAM Timing: SW = 1 Cycle, HW = 1 Cycle, One Asynchronous
External Wait Cycle, CSnWCR.BAS = 1 (WE-Controlled Write Cycle) ............. 748
Figure 25.16 Synchronous DRAM Single Read Bus Cycle
(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 0 Cycle)...... 749
Figure 25.17 Synchronous DRAM Single Read Bus Cycle
(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 1 Cycle)....... 750
Figure 25.18 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 0 Cycle, WTRP = 1 Cycle)....... 751
Figure 25.19 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Auto-Precharge, CAS Latency = 2, WTRCD = 1 Cycle, WTRP = 0 Cycle)....... 752
Figure 25.20 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, TRWL = 1 Cycle) ..................................................................... 753
Figure 25.21 Synchronous DRAM Single Write Bus Cycle
(Auto-Precharge, WTRCD = 2 Cycles, TRWL = 1 Cycle)................................... 754
Figure 25.22 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 0 Cycle, TRWL = 1 Cycle) .................................... 755
Figure 25.23 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Auto-Precharge, WTRCD = 1 Cycle, TRWL = 1 Cycle) .................................... 756
Figure 25.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4) (Bank Active Mode:
ACT + READ Commands, CAS Latency = 2, WTRCD = 0 Cycle)..................... 757
Figure 25.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency = 2,
WTRCD = 0 Cycle) .............................................................................................. 758
Figure 25.26 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
(Bank Active Mode: PRE + ACT + READ Commands, Different Row Addresses,
CAS Latency = 2, WTRCD = 0 Cycle)................................................................. 759
Figure 25.27 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: ACT + WRITE Commands, WTRCD = 0 Cycle,
TRWL = 0 Cycle).................................................................................................. 760
Figure 25.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: WRITE Command, Same Row Address, WTRCD = 0 Cycle,
TRWL = 0 Cycle).................................................................................................. 761
Figure 25.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
WTRCD = 0 Cycle, TRWL = 0 Cycle)................................................................. 762
Figure 25.30 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles) ................................................................. 763
Figure 25.31 Synchronous DRAM Self-Refreshing Timing (WTRP = 1 Cycle) ....................... 764
Rev. 6.00 Jul. 15, 2009 Page xxx of xxxviii