SH7619_09 Datasheet, PDF (102/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
(1) Address array access
(a) Address specification
Read access
31
1111 0000
24 23
Write access
31
1111 0000
24 23
*--------*
*--------*
14 13 12 11
43210
W Entry address 0 * 0 0
14 13 12 11
43210
W Entry address A * 0 0
(b) Data specification (both read and write accesses)
31 30 29 28
00 0
Tag address (28 to 10)
10 9
LRU
43210
X XU V
(2) Data array access (both read and write accesses)
(a) Address specification
31
24 23
1111 0001
*--------*
14 13 12 11
43210
W Entry address L 0 0
(b) Data specification
31
0
Longword
[Legend]
*: Don't care
X: 0 for read, don't care for write
Figure 3.4 Specifying Address and Data for Memory-Mapped Cache Access
Rev. 6.00 Jul. 15, 2009 Page 62 of 816
REJ09B0237-0600