SH7619_09 Datasheet, PDF (93/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 3 Cache
Section 3 Cache
3.1 Features
• Capacity: 16 kbytes
• Structure: Instructions/data unified, 4-way set associative
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode
• Write method: Write-back/write-through is selectable
• Replacement method: Least-recently-used (LRU) algorithm
3.1.1 Cache Structure
The cache holds both instructions and data and employs a 4-way set associative system. It is
composed of four ways (banks), and each of which is divided into an address section and a data
section. Each of the address and data sections is divided into 256 entries. The data of an entry is
called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes
(16 bytes × 256 entries), with a total of 16 kbytes in the cache (4 ways).
Figure 3.1 shows the cache structure.
Address array (ways 0 to 3)
Data array (ways 0 to 3)
LRU
Entry 0 _{V U Tag address}
0 _{LW0 LW1 LW2 LW3}
0
Entry 1
1
1
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Entry 255
24 (1 + 1 + 22) bits
255
128 (32 × 4) bits
LW0 to LW3: Longword data 0 to 3
Figure 3.1 Cache Structure
255
6 bits
Rev. 6.00 Jul. 15, 2009 Page 53 of 816
REJ09B0237-0600