SH7619_09 Datasheet, PDF (512/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame (slot number).
Initial
Bit
Bit Name Value R/W Description
15
RDLE
0
R/W Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
14 to 12 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
11
RDLA3 0
R/W Receive Left-Channel Data Assigns 3 to 0
10
RDLA2 0
R/W Specify the position of left-channel data in a receive
9
RDLA1 0
R/W ^{frame as B'0000 (0) to B'1110 (14).}
8
RDLA0 0
R/W ^{1111: Setting prohibited}
• Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
7
RDRE
0
R/W Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
6 to 4 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
RDRA3 0
R/W Receive Right-Channel Data Assigns 3 to 0
2
RDRA2 0
R/W Specify the position of right-channel data in a receive
1
RDRA1 0
R/W ^{frame as B'0000 (0) to B'1110 (14).}
0
RDRA0 0
R/W ^{1111: Setting prohibited}
• Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
Rev. 6.00 Jul. 15, 2009 Page 472 of 816
REJ09B0237-0600