SH7619_09 Datasheet, PDF (439/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
Table 15.2 SCSMR Settings
SCSMR Settings
n
Clock Source
CKS1
CKS0
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Note: The bit rate error in asynchronous is given by the following formula:
Error (%) =
Pφ × 10⁶
- 1 × 100
(N + 1) × B × 64^2n-1 × 2
Table 15.3 lists examples of SCBRR settings in asynchronous mode, and table 15.4 lists examples
of SCBRR settings in synchronous mode.
Table 15.3 Bit Rates and SCBRR Settings in Asynchronous Mode
Bit Rate (bits/s) n
110
2
150
2
300
1
600
1
1200
0
2400
0
4800
0
9600
0
19200
0
31250
0
38400
0
5
N
Error (%) n
88
–0.25 2
64
0.16
2
129 0.16
1
64
0.16
1
129 0.16
0
64
0.16
0
32
–1.36 0
15
1.73
0
7
1.73
0
4
0.00
0
3
1.73
0
Pφ (MHz)
6
N
Error (%) n
106 –0.44 2
77
0.16
2
155 0.16
1
77
0.16
1
155 0.16
0
77
0.16
0
38
0.16
0
19
–2.34 0
9
–2.34 0
5
0.00
0
4
–2.34 0
6.144
N
Error (%)
108 0.08
79 0.00
159 0.00
79 0.00
159 0.00
79 0.00
39 0.00
19 0.00
9
0.00
5
2.40
4
0.00
Rev. 6.00 Jul. 15, 2009 Page 399 of 816
REJ09B0237-0600