SH7619_09 Datasheet, PDF (671/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 22 Ethernet Physical Layer Transceiver (PHY)
Section 22 Ethernet Physical Layer Transceiver (PHY)
This LSI has an on-chip PHY module.
22.1 Features
• Fully-integrated IEEE 802.3/802.3u compliant 10/100Mbps Ethernet PHY
• PHY clock = 25 MHz, 3.3 V Analog power supply.
• Integrated DSP with adaptive-equalizer and Baseline Wander (BLW) correction High
immunity to crosstalk
• Link-configuration automatically determined by Auto-negotiation / parallel detection; manual
configuration also available
• Low power consumption
• Half- and Full-duplex capable for both 10 and 100 Mbps links
• Automatic Polarity Correction in 10Base-T
• Extended cable length option in 10Base-T
• MII interface to the CPU core of this LSI.
• Serial Management Interface (SMI)
• Link, Activity, Duplex and Speed LED outputs
Rev. 6.00 Jul. 15, 2009 Page 631 of 816
REJ09B0237-0600