SH7619_09 Datasheet, PDF (540/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
[Notes on Usage]
1. Defect in Frame Synchronous Signal (SYNC) Length
(a) Phenomena
With the SIOF Master Mode 2, in some case, the length of the SYNC signal in high level error
occurs by changing the SYNC signal output condition from disabled (the FSE bit = 0) to
enabled (the FSE bit = 1). In the above case, the SYNC signal rises before the correct timing
and the length of the signal in high level will be 1 bit longer in the first frame than the value set
in the SIMDR, whereas the error DOES NOT occur after second frame.
SYNC
In the first frame, the length of the SYNC signal in high level is 1 bit
longer than the value set in the SIMDR.
17 bits
16 bits
16 bits
16 bits
TxD
32 bits (valid data)
32 bits (valid data)
1 bit
(Example): With the SIOF Master Mode 2, Frame Length = 32 bits
(b) Defect prevention
*Please take following procedures (i) or (ii).
(i) In the case of setting a data, please write a dummy data for the first frame and the valid
data for other frames into the transmit FIFO, and set the destination stations to discard
the data in the first frame.
(ii) In the use of this product, please make your system composition that works correctly
even in the case that the length of the SYNC signal will be 1 bit longer.
2. Resume Data Transmission with the SIOF Master Mode
(a) Defect data transmission
With the SIOF master mode, in some case, the data is NOT transmitted correctly when the
transmission operation is resumed after stopping the previous transmission operation by setting
‘0’ to the TXE bit.
Rev. 6.00 Jul. 15, 2009 Page 500 of 816
REJ09B0237-0600