SH7619_09 Datasheet, PDF (385/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 13 Direct Memory Access Controller (DMAC)
When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer
destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer
request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive
data register. These conditions also apply to the SCIF1, SCIF2, and SIOF0.
The number of the receive FIFO triggers can be set as a transfer request depending on an on-chip
peripheral module. Data needs to be read after the DMA transfer is ended, because data may be
remained in the receive FIFO when the receive FIFO trigger condition is not satisfied.
Table 13.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
RS[3:0]
1000
DMARS
MID
RID
001000 01
10
001001 01
10
001010 01
10
010100 01
10
DMA Transfer
Request
DMA Transfer
Source
Request Signal
SCIF0
transmitter
TXI0 (transmit FIFO data
empty interrupt)
SCIF0
receiver
RXI0 (receive FIFO data
full interrupt)
SCIF1
transmitter
TXI1 (transmit FIFO data
empty interrupt)
SCIF1
receiver
RXI1 (receive FIFO data
full interrupt)
SCIF2
transmitter
TXI2 (transmit FIFO data
empty interrupt)
SCIF2
receiver
RXI2 (receive FIFO data
full interrupt)
SIOF0
transmitter
TXI0 (transmit FIFO data
empty interrupt)
SIOF0
receiver
RXI0 (receive FIFO data
full interrupt)
Source
Any
SCFRDR0
Any
SCFRDR1
Any
SCFRDR2
Any
SIRDR0
Destination
SCFTDR0
Any
SCFTDR0
Any
SCFTDR2
Any
SITDR0
Any
Bus
Mode
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
Cycle
steal
13.4.3 Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it transfers
data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are
selected by the PR1 and PR0 bits in DMAOR.
Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are two
kinds of fixed modes as follows:
• CH0 > CH1 > CH2 > CH3
• CH0 > CH2 > CH3 > CH1
These are selected by the PR1 and the PR0 bits in DMAOR.
Rev. 6.00 Jul. 15, 2009 Page 345 of 816
REJ09B0237-0600