SH7619_09 Datasheet, PDF (42/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 1 Overview
1.1 Features
The features of this LSI are listed in table 1.1.
Table 1.1 Features of SH7619
Items
CPU
User break controller
(UBC)
U memory
Cache memory
Specification
• Central processing unit with an internal 32-bit RISC (Reduced
Instruction Set Computer) architecture
• Instruction length: 16-bit fixed length for improved code efficiency
• Load-store architecture (basic operations are executed between
registers)
• Sixteen 32-bit general registers
• Five-stage pipeline
• On-chip multiplier: Multiplication operations (32 bits × 32 bits → 64 bits)
executed in two to five cycles
• C language-oriented 62 basic instructions
Note:
Some specifications on the slot illegal instruction differ from the
conventional SH2 core. For details, see section 5.8, Usage
Notes in section 5, Exception Handling.
• Address, data value, access type, and data size are available for
setting as break conditions
• Supports the sequential break function
• Two break channels
• 16 kbytes
• Unified cache, mixture of instructions and data
• 4-way set associative type
• Selection of write-back or write-through mode
• 16 kbytes
Rev. 6.00 Jul. 15, 2009 Page 2 of 816
REJ09B0237-0600