SH7619_09 Datasheet, PDF (36/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 7 Bus State Controller (BSC)
Table 7.1 Pin Configuration.................................................................................................. 110
Table 7.2 Address Map 1 (CMNCR.MAP = 0) .................................................................... 113
Table 7.3 Address Map 2 (CMNCR.MAP = 1) .................................................................... 113
Table 7.4 Correspondence between External Pin (MD3),
Memory Type, and Bus Width for CS0 ................................................................ 114
Table 7.5 Correspondence between External Pin (MD5) and Endians................................. 114
Table 7.6 32-Bit External Device/Big Endian Access and Data Alignment......................... 143
Table 7.7 16-Bit External Device/Big Endian Access and Data Alignment......................... 144
Table 7.8 8-Bit External Device/Big Endian Access and Data Alignment........................... 145
Table 7.9 32-Bit External Device/Big Endian Access and Data Alignment......................... 146
Table 7.10 16-Bit External Device/Little Endian Access and Data Alignment ...................... 147
Table 7.11 8-Bit External Device/Little Endian Access and Data Alignment ........................ 148
Table 7.12 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (1) ................................................. 160
Table 7.13 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (2) ................................................. 161
Table 7.14 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (3) ................................................. 163
Table 7.15 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (4) ................................................. 164
Table 7.16 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (5) ................................................. 165
Table 7.17 Relationship between Register Settings (BSZ[1:0], A3ROW[1:0], and
A3COL[1:0]) and Address Multiplex Output (6) ................................................. 167
Table 7.18 Relationship between Access Size and Number of Bursts.................................... 169
Table 7.19 Access Address for SDRAM Mode Register Write.............................................. 185
Section 8 Clock Pulse Generator (CPG)
Table 8.1 Pin Configuration.................................................................................................. 204
Table 8.2 Mode Control Pins and Clock Operating Modes .................................................. 204
Table 8.3 Possible Combination of Clock Modes and FRQCR Values................................ 205
Section 10 Power-Down Modes
Table 10.1 States of Power-Down Modes .............................................................................. 223
Table 10.2 Pin Configuration.................................................................................................. 224
Table 10.3 Register States in Software Standby Mode........................................................... 230
Section 11 Ethernet Controller (EtherC)
Table 11.1 Pin Configuration.................................................................................................. 235
Rev. 6.00 Jul. 15, 2009 Page xxxiv of xxxviii