SH7619_09 Datasheet, PDF (483/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
9. Clear Timing of the FER or PER Bits when the DMAC Saves the Receive Data in
Asynchronous Mode
The FER or PER bits in SCFSR are set when data including a framing error or parity error is
received in asynchronous mode, whereas cleared when the corresponding data is read from
SCFRDR. Therefore, when data with an error is received while the DMAC is set to save the
receive data automatically, the receive-error interrupt is accepted after the DMAC reads the
corresponding data. As a result, the CPU cannot check the FER or PER bits.
To prevent this defect, the RTRG[1:0] bits in SCFCR should be set to the higher number to
delay the DMAC call timing. This enables the CPU to check the FER or PER bits in the
receive-error interrupt routine, prior to the DMAC to read the error data.
Rev. 6.00 Jul. 15, 2009 Page 443 of 816
REJ09B0237-0600