SH7619_09 Datasheet, PDF (538/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
16-bit Stereo Data (2): L/R method, rising edge sampling, slot No.0 used for left-channel
transmit data, slot No.1 used for left-channel receive data, slot No.2 used for right-channel
transmit data, slot No.3 used for right-channel receive data, and frame length = 64 bits
SIOFSCK
SIOFSYNC
SIOFTxD
L-channel data
1 frame
R-channel data
SIOFRxD
Slot No.0
L-channel data
Slot No.1
Slot No.2
R-channel data
Slot No.3
No bit delay
Specifications: _{TRMD[1:0]=01,} REDG=1,
TDLE=1,
TDLA[3:0]=0000,
RDLE=1,
RDLA[3:0]=0001,
CD0E=0,
CD0A[3:0]=0000,
FL[3:0]=1101 (frame length: 64 bits),
TDRE=1,
TDRA[3:0]=0010,
RDRE=1,
RDRA[3:0]=0011,
CD1E=0,
CD1A[3:0]=0000
Figure 16.17 Transmit and Receive Timing (16-Bit Stereo Data (2))
16-bit Stereo Data (3): Synchronous pulse method, falling edge sampling, slot No.0 used for left-
channel data, slot No.1 used for right-channel data, slot No.2 used for control channel 0 data, slot
No.3 used for control channel 1 data, and frame length = 128 bits
1 frame
SIOFSCK
SIOFSYNC
SIOFTxD
SIOFRxD
L-channel R-channel Control Control
data
data channel 0 channel 1
Slot No.0 Slot No.1 Slot No.2 Slot No.3 Slot No.4 Slot No.5 Slot No.6 Slot No.7
1 bit delay
Specifications: TRMD[1:0]=00 or 10,REDG=0,
TDLE=1,
TDLA[3:0]=0000,
RDLE=1,
RDLA[3:0]=0000,
CD0E=1,
CD0A[3:0]=0010,
FL[3:0]=1110 (frame length: 128 bits),
TDRE=1,
TDRA[3:0]=0001,
RDRE=1,
RDRA[3:0]=0001,
CD1E=1,
CD1A[3:0]=0011
Figure 16.18 Transmit and Receive Timing (16-Bit Stereo Data (3))
Rev. 6.00 Jul. 15, 2009 Page 498 of 816
REJ09B0237-0600