SH7619_09 Datasheet, PDF (491/860 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7619 Series

Section 16 Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value
4
SYNCDL 0
3 to 0 
All 0
R/W
R/W
R
Description
Data Pin Bit Delay for SIOFSYNC Pin
Valid when the SIOFSYNC signal is output as
synchronous pulse. Only one-bit delay is valid for
transmission in slave mode.
0: No bit delay
1: 1-bit delay
Reserved
These bits are always read as 0. The write value should
always be 0.
Table 16.2 Operation in Each Transfer Mode
Transfer Mode Master/Slave SIOFSYNC
Bit Delay
Control Data Method*
Slave mode 1
Slave
Synchronous
pulse
SYNCDL bit
Slot position
Slave mode 2
Slave
Synchronous
pulse
Secondary FS
Master mode 1 Master
Synchronous
pulse
Slot position
Master mode 2 Master
L/R
No
Not supported
Note: * The control data method is valid only when the FL3 to FL0 bits are specified as 1xxx. (x:
Don’t care.)
Rev. 6.00 Jul. 15, 2009 Page 451 of 816
REJ09B0237-0600